1. Technical Field
The present invention relates to DRAM (Dynamic Random Access Memory) cells, and more particularly, to DRAM cells with self-aligned gradient wells.
2. Related Art
In a typical trench DRAM cell there exists a VPT (vertical parasitic transistor) that causes a leakage current during the normal operating of the DRAM cell. Therefore, there is a need for a structure and a method for forming the same of a DRAM cell in which the leakage current flowing through the VPT is reduced without compromising other device characteristics.